View MBM29PDS322BE11PBT-E1_3873892.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mbm29pds322te 10/11 / mbm29pds322be 10/11 mbm29pds322te 10/11 /mbm29pds322be 10/11 cover sheet data sheet (retired product) this product has been retired and is not recommended for new designs . availability of this document is retained for reference and historical purposes only. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansi on product. any changes that have been made are the result of normal data sheet improvem ent and are noted in the document revision summary. for more information please contact your local sales office for additional information about spansion memory solutions. publication number mbm29pds322te/be revision ds05-20889-6e issue date july 31, 2007
this page left intentionally blank. 2 mbm29pds322te/be_ds05-20889-6e july 31, 2007 data sheet (retired product)
september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and ch anges will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20889-6e fujitsu semiconductor data sheet retired product y ds05-20889-6e_july 31, 2007 flash memory cmos 32m (2m 16) bit page dual operation mbm29pds322te 10/11 mbm29pds322be 10/11 description the mbm29pds322te/be is 32m-bit, 1.8 v-only flash me mory organized as 2m words of 16 bits each. the device is offered in 63-ball fbga package. this device is designed to be programmed in system with standard system 1.8 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the device is organized into two banks, bank 1 and bank 2, which are considered to be two separate memory arrays for operations are concerned. it is the fujitsu?s standard 1.8 v only flash memories with the additional capability of allowing a normal non- delayed read access fr om a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. (continued) product line-up pac k ag e part no. mbm29pds322te/be 10 11 power supply voltage v cc (v) 2.0 v max random address access time (ns) 100 115 max page address access time (ns) 40 50 max ce access time (ns) 100 115 max oe access time (ns) 35 45 +0.2 v ?0.2 v 63-ball plastic fbga (bga-63p-m01)
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 5 (continued) the device provides truly high performance non-volatile flash memory solution. the device offers fast page access times of 45 ns with random access times of 100 ns and 115 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the page size is 4 words. the device is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timi ngs. register contents serve as input to an internal state-machine which controls the erase and programming ci rcuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the progra m command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence . this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically time the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 1.8 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. the device also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the ad dress locations being programme d or erased. these locations need re-writing after the reset. resetting the device enables the system?s microprocessor to read the boot-up firmware from the flash memory. fujitsu?s flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiven ess. the device memory electrically er ase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the words are programmed one word at a time using the eprom programming mechanism of hot electron injection.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 6 features ? 0.23 m process technology ? simultaneous read/write operations (dual bank) host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. read-while-erase read-while-program ? high performance page mode 45 ns maximum page access time (100 ns random access time) 4 words page size ? single 1.8 v read, program, and erase minimized system level power requirements ? compatible with je dec-standard commands use the same software commands as e 2 proms. ? compatible with jedec-standard world-wide pinouts 63-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles ? sector erase architecture eight 4 k word and sixty-three 32 k word sectors in word mode any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? hiddenrom region 32 k word of hiddenrom, accessible through a new ?hiddenrom enable? command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of boot sectors, regardless of sector protection/unprotection status. at v acc , increases program performance. ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector. ? embedded program tm * algorithms automatically writes and verifies data at specified address. ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device. ? sector group protection hardware method disables any combination of sector groups from program or erase operations. ? sector group protection set function by extended sector group protection command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin. * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 7 mbm29pds322te/be device bank division device part number organization bank 1 bank 2 megabits sector sizes megabits sector sizes mbm29pds322te/be 16 4 mbit eight 4 k word, seven 32 k word 28 mbit fifty-six 32 k word
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 8 pin assignment (top view) (bga-63p-m01) a8 b8 n.c. * n.c. * n.c. * n.c. * a7 b7 c7 d7 e7 f7 g7 h7 j7 k7 c6 d6 e6 f6 g6 h6 j6 k6 a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 c5 d5 e5 f5 g5 h5 j5 k5 we reset n.c. a 19 dq 5 dq 12 v cc dq 4 c4 d4 e4 f4 g4 h4 j4 k4 ry/by wp/acc a 18 a 20 dq 2 dq 10 dq 11 dq 3 c3 d3 e3 f3 g3 h3 j3 k3 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 a 3 a2 n.c. * a1 n.c. * b1 n.c. * a 4 a 2 a 1 a 0 ce oe v ss l7 l8 m7 a 13 a 12 a 14 a 15 a 16 dq 15 v ss n.c. * n.c. * m8 n.c. * n.c. * l1 n.c. * m1 n.c. * n.c. * n.c. * n.c. (marking side) *: peripheral balls on each corner are shorted together via the substrate but not connected to the die.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 9 pin description mbm29pds322te/be pin configuration pin name function a 20 to a 0 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector group unprotection wp /acc hardware write protection/program acceleration n.c. no internal connection v ss device ground v cc device power supply
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 10 block diagram logic symbol v cc v ss a 20 to a 0 reset we ce oe wp/acc dq 15 to dq 0 dq 15 to dq 0 bank 2 address bank 1 address state control & command register status ry/by control cell matrix (bank 2) x-decoder y-gating cell matrix (bank 1) x-decoder y-gating 21 a 20 to a 0 we oe ce dq 15 to dq 0 16 wa/acc reset ry/by
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 11 device bus operation mbm29pds322te/be user bus operations table legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see ? dc characteristics? for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see ?mbm29pds322te/be user bus operations? table. *2: refer to section on sector group protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc must be between the minimum and maximum of the operation range. *5: also used for the extended sector group protection. *6: protect ?outermost? 2 4 k words of the boot block sectors. operation ce oe we a 0 a 1 a 2 a 3 a 6 a 9 dq 15 to dq 0 reset wp / acc auto-select manufacturer code * 1 llhlllllv id code h x auto-select device code * 1 llhhllllv id code h x extended auto-select device code * 1 l lhl/hhhhlv id code h x read * 3 llha 0 a 1 a 2 a 3 a 6 a 9 d out hx standby h x x x x x x x x high-z h x output disable l h h x x x x x x high-z h x write (program/erase) l h l a 0 a 1 a 2 a 3 a 6 a 9 d in hx enable sector group protection * 2, * 4 lv id lhlllv id xhx verify sector group protection * 2, * 4 llhlhlllv id code h x temporary sector group unprotection * 5 xxxxxxxxx x v id x reset (hardware) / standby x x x x x x x x x high-z l x boot block sector write protection * 6 xxxxxxxxx x x l
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 12 mbm29pds322te/be command definitions table *1: this command is valid during fast mode. *2: this command is valid while reset = v id . *3: this command is valid during hiddenrom mode. *4: the data ?00h? is also acceptable. notes : ? address bits a 20 to a 12 = x = ?h? or ?l? for all address commands except or program address (pa), sector address (sa), and bank address (ba). ? bus operations are defined in ?simultaneous operation table? in ? functional description?. ? ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 20 to a 15 ) command sequence bus write cycles req?d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/resetword1xxxhf0h?????????? read/reset word 3 555h aah 2aah 55h 555h f0h ra rd ? ? ? ? auto select word 3 555h aah 2aah 55h (ba) 555h 90h?????? program word 4 555h aah 2aah 55h 555h a0h pa pd ? ? ? ? chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h erase suspend 1 ba b0h ? ? ? ? ? ? ? ? ? ? erase resume 1 ba30h?????????? set to fast mode word 3 555h aah 2aah 55h 555h 20h ? ? ? ? ? ? fast program * 1 word2xxxha0hpapd???????? reset from fast mode * 1 word 2 ba 90h xxxh * 4 f0h ???????? extended sector group protection * 2 word 4 xxxh 60h spa 60h spa 40h spa sd ? ? ? ? hiddenrom entry word 3 555h aah 2aah 55h 555h 88h ? ? ? ? ? ? hiddenrom program * 3 word 4 555h aah 2aah 55h 555h a0h (hra) pa pd???? hiddenrom erase * 3 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h hiddenrom exit * 3 word 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h ? ? ? ?
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 13 ? rd = data read from location ra during the read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. ? spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. ? hra = address of the hiddenrom area 29pds322te (top boot type)word mode:1f8000h to 1fffffh 29pds322be (bottom boot type)word mode:000000h to 007fffh ? hrba =bank address of the hiddenrom area 29pds322te (top boot type):a 20 = a 19 = a 18 = a 17 = a 16 = a 15 = 1 29pds322be (bottom boot type):a 20 = a 19 = a 18 = a 17 = a 16 = a 15 = 0 ? the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 10 to a 0 ? both read/reset commands are functionally equivalent, resetting the device to the read mode. ? the command combinations not described mbm2 9pds322te/be command de finitions are illegal.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 14 mbm29pds322te sector group protecti on verify autoselect codes table *1 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : when v id is applied, both bank 1 and bank 2 become autoselect mode, which leads to the simultaneous operation unable to be executed. consequently, specif ying the bank address is not demanded. however, the bank address needs to be indicated when autoselect mode is read out at command mode; because then it becomes ok to activate simultaneous operation. *3 : a read cycle at address (ba)01h outputs device code. when 227eh was output, this indicates that there will require two additional codes, called extended device codes. therefore, the system may continue reading out these extended device codes at the addres s of (ba)0eh, as well as at (ba)0fh. expanded autoselect code table (w): word mode type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufacture?s code ba *2 v il v il v il v il v il 04h device code word ba *2 v il v il v il v il v ih 227eh extended device code * 3 word ba *2 v il v ih v ih v ih v il 2206h word ba *2 v il v ih v ih v ih v ih 2201h sector group protection sector group addresses v il v il v il v ih v il 01h *1 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer?s code 04h000000 0000000100 device code (w) 227eh 001000 1001111110 extended device code (w) 2206h 001000 1000000110 (w) 2201h 001000 1000000001 sector group protection 01h000000 0000000001
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 15 mbm29pds322be sector group protection verify autoselect codes table *1 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : when v id is applied, both bank 1 and bank 2 become autoselect mode, which leads to the simultaneous operation unable to be executed. consequently, specif ying the bank address is not demanded. however, the bank address needs to be indicated when autoselect mode is read out at command mode; because then it becomes ok to activate simultaneous operation. * 3 : a read cycle at address (ba)01h outputs device code. when 227eh was output, this indica tes that there will require two additional codes, called extended device codes. therefore, the system may continue reading out these extended device codes at the addres s of (ba)0eh, as well as at (ba)0fh. expanded autoselect code table (w): word mode type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufacture?s code ba *2 v il v il v il v il v il 04h device code word ba *2 v il v il v il v il v ih 227eh extended device code * 3 word ba *2 v il v ih v ih v ih v il 2206h word ba *2 v il v ih v ih v ih v ih 2200h sector group protection sector group addresses v il v il v il v ih v il 01h *1 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer?s code 04h0000000 000000100 device code (w) 227eh 0010001 001111110 extended device code (w) 2206h 0010001 000000110 (w) 2200h 0010001 000000000 sector group protection 01h0000000 000000001
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 16 flexible sector-erase architecture sector address table (mbm29pds322te) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa0 000000xxx 32 000000h to 007fffh sa1 000001xxx 32 008000h to 00 ffffh sa2 000010xxx 32 010000h to 017fffh sa3 000011xxx 32 018000h to 01 ffffh sa4 000100xxx 32 020000h to 027fffh sa5 000101xxx 32 028000h to 02 ffffh sa6 000110xxx 32 030000h to 037fffh sa7 000111xxx 32 038000h to 03 ffffh sa8 001000xxx 32 040000h to 047fffh sa9 001001xxx 32 048000h to 04 ffffh sa10001010xxx 32 050000h to 057fffh sa11001011xxx 32 058000h to 05 ffffh sa12001100xxx 32 060000h to 067fffh sa13001101xxx 32 068000h to 06 ffffh sa14001110xxx 32 070000h to 077fffh sa15001111xxx 32 078000h to 07 ffffh sa16010000xxx 32 080000h to 087fffh sa17010001xxx 32 088000h to 08 ffffh sa18010010xxx 32 090000h to 097fffh sa19010011xxx 32 098000h to 09 ffffh sa20010100xxx 32 0a0000h to 0a7 fffh sa21010101xxx 32 0a8000h to 0affffh sa22010110xxx 32 0b0000h to 0b7 fffh sa23010111xxx 32 0b8000h to 0bffffh sa24011000xxx 32 0c0000h to 0c7 fffh sa25011001xxx 32 0c8000h to 0cffffh sa26011010xxx 32 0d0000h to 0d7 fffh sa27011011xxx 32 0d8000h to 0dffffh sa28011100xxx 32 0e0000h to 0e7 fffh sa29011101xxx 32 0e8000h to 0effffh sa30011110xxx 32 0f0000h to 0f7fffh sa31011111xxx 32 0f8000h to 0ff fffh sa32100000xxx 32 100000h to 107fffh sa33100001xxx 32 108000h to 10 ffffh sa34100010xxx 32 110000h to 117fffh
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 17 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa35100011xxx 32 118000h to 11 ffffh sa36100100xxx 32 120000h to 127fffh sa37100101xxx 32 128000h to 12 ffffh sa38100110xxx 32 130000h to 137fffh sa39100111xxx 32 138000h to 13 ffffh sa40101000xxx 32 140000h to 147fffh sa41101001xxx 32 148000h to 14 ffffh sa42101010xxx 32 150000h to 157fffh sa43101011xxx 32 158000h to 15 ffffh sa44101100xxx 32 160000h to 167fffh sa45101101xxx 32 168000h to 16 ffffh sa46101110xxx 32 170000h to 177fffh sa47101111xxx 32 178000h to 17 ffffh sa48110000xxx 32 180000h to 187fffh sa49110001xxx 32 188000h to 18 ffffh sa50110010xxx 32 190000h to 197fffh sa51110011xxx 32 198000h to 19 ffffh sa52110100xxx 32 1a0000h to 1a7 fffh sa53110101xxx 32 1a8000h to 1affffh sa54110110xxx 32 1b0000h to 1b7 fffh sa55110111xxx 32 1b8000h to 1bffffh bank 1 sa56111000xxx 32 1c0000h to 1c7 fffh sa57111001xxx 32 1c8000h to 1cffffh sa58111010xxx 32 1d0000h to 1d7 fffh sa59111011xxx 32 1d8000h to 1dffffh sa60111100xxx 32 1e0000h to 1e7 fffh sa61111101xxx 32 1e8000h to 1effffh sa62111110xxx 32 1f0000h to 1f7fffh sa63111111000 4 1f8000h to 1f8fffh sa64111111001 4 1f9000h to 1f9fffh sa65111111010 4 1fa000h to 1fa fffh sa66111111011 4 1fb000h to 1fb fffh sa67111111100 4 1fc000h to 1fcfffh sa68111111101 4 1fd000h to 1fdfffh sa69111111110 4 1fe000h to 1fe fffh sa70111111111 4 1ff000h to 1 fffffh
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 18 sector address table (mbm29pds322be) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa70111111xxx 32 1f8000h to 1ff fffh sa69111110xxx 32 1f0000h to 1f7fffh sa68111101xxx 32 1e8000h to 1effffh sa67111100xxx 32 1e0000h to 1e7 fffh sa66111011xxx 32 1d8000h to 1dffffh sa65111010xxx 32 1d0000h to 1d7 fffh sa64111001xxx 32 1c8000h to 1cffffh sa63111000xxx 32 1c0000h to 1c7 fffh sa62110111xxx 32 1b8000h to 1bffffh sa61110110xxx 32 1b0000h to 1b7 fffh sa60110101xxx 32 1a8000h to 1affffh sa59110100xxx 32 1a0000h to 1a7 fffh sa58110011xxx 32 198000h to 19 ffffh sa57110010xxx 32 190000h to 197fffh sa56110001xxx 32 188000h to 18 ffffh sa55110000xxx 32 180000h to 187fffh sa54101111xxx 32 178000h to 17 ffffh sa53101110xxx 32 170000h to 177fffh sa52101101xxx 32 168000h to 16 ffffh sa51101100xxx 32 160000h to 167fffh sa50101011xxx 32 158000h to 15 ffffh sa49101010xxx 32 150000h to 157fffh sa48101001xxx 32 148000h to 14 ffffh sa47101000xxx 32 140000h to 147fffh sa46100111xxx 32 138000h to 13 ffffh sa45100110xxx 32 130000h to 137fffh sa44100101xxx 32 128000h to 12 ffffh sa43100100xxx 32 120000h to 127fffh sa42100011xxx 32 118000h to 11 ffffh sa41100010xxx 32 110000h to 117fffh sa40100001xxx 32 108000h to 10 ffffh sa39100000xxx 32 100000h to 107fffh sa38011111xxx 32 0f8000h to 0ff fffh sa37011110xxx 32 0f0000h to 0f7fffh sa36011101xxx 32 0e8000h to 0effffh sa35011100xxx 32 0e0000h to 0e7 fffh
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 19 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa34011011xxx 32 0d8000h to 0dffffh sa33011010xxx 32 0d0000h to 0d7 fffh sa32011001xxx 32 0c8000h to 0cffffh sa31011000xxx 32 0c0000h to 0c7 fffh sa30010111xxx 32 0b8000h to 0bffffh sa29010110xxx 32 0b0000h to 0b7 fffh sa28010101xxx 32 0a8000h to 0affffh sa27010100xxx 32 0a0000h to 0a7 fffh sa26010011xxx 32 098000h to 09 ffffh sa25010010xxx 32 090000h to 097fffh sa24010001xxx 32 088000h to 08 ffffh sa23010000xxx 32 080000h to 087fffh sa22001111xxx 32 078000h to 07 ffffh sa21001110xxx 32 070000h to 077fffh sa20001101xxx 32 068000h to 06 ffffh sa19001100xxx 32 060000h to 067fffh sa18001011xxx 32 058000h to 05 ffffh sa17001010xxx 32 050000h to 057fffh sa16001001xxx 32 048000h to 04 ffffh sa15001000xxx 32 040000h to 047fffh bank 1 sa14000111xxx 32 038000h to 03 ffffh sa13000110xxx 32 030000h to 037fffh sa12000101xxx 32 028000h to 02 ffffh sa11000100xxx 32 020000h to 027fffh sa10000011xxx 32 018000h to 01 ffffh sa9 000010xxx 32 010000h to 017fffh sa8 000001xxx 32 008000h to 00 ffffh sa7 000000111 4 007000h to 007fffh sa6 000000110 4 006000h to 006fffh sa5 000000101 4 005000h to 005fffh sa4 000000100 4 004000h to 004fffh sa3 000000011 4 003000h to 003fffh sa2 000000010 4 002000h to 002fffh sa1 000000001 4 001000h to 001fffh sa0 000000000 4 000000h to 000fffh
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 20 sector group address table (mbm29pds322te) (top boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0 0 0 0 0 0 x x x sa0 sga1 0 0 0 0 01 x x x sa1 to sa3 10 11 sga2 0 0 0 1 x x x x x sa4 to sa7 sga3 0 0 1 0 x x x x x sa8 to sa11 sga4 0 0 1 1 x x x x x sa12 to sa15 sga5 0 1 0 0 x x x x x sa16 to sa19 sga6 0 1 0 1 x x x x x sa20 to sa23 sga7 0 1 1 0 x x x x x sa24 to sa27 sga8 0 1 1 1 x x x x x sa28 to sa31 sga9 1 0 0 0 x x x x x sa32 to sa35 sga10 1 0 0 1 x x x x x sa36 to sa39 sga11 1 0 1 0 x x x x x sa40 to sa43 sga12 1 0 1 1 x x x x x sa44 to sa47 sga13 1 1 0 0 x x x x x sa48 to sa51 sga14 1 1 0 1 x x x x x sa52 to sa55 sga15 1 1 1 0 x x x x x sa56 to sa59 sga16 1 1 1 1 00 x x x sa60 to sa62 01 10 sga17 111111000 sa63 sga18 111111001 sa64 sga19 111111010 sa65 sga20 111111011 sa66 sga21 111111100 sa67 sga22 111111101 sa68 sga23 111111110 sa69 sga24 111111111 sa70
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 21 sector group address table (mbm29pds322be) (bottom boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 sga8 0 0 0 0 01 x x x sa8 to sa10 10 11 sga9 0 0 0 1 x x x x x sa11 to sa14 sga10 0 0 1 0 x x x x x sa15 to sa18 sga11 0 0 1 1 x x x x x sa19 to sa22 sga12 0 1 0 0 x x x x x sa23 to sa26 sga13 0 1 0 1 x x x x x sa27 to sa30 sga14 0 1 1 0 x x x x x sa31 to sa34 sga15 0 1 1 1 x x x x x sa35 to sa38 sga16 1 0 0 0 x x x x x sa39 to sa42 sga17 1 0 0 1 x x x x x sa43 to sa46 sga18 1 0 1 0 x x x x x sa47 to sa50 sga19 1 0 1 1 x x x x x sa51 to sa54 sga20 1 1 0 0 x x x x x sa55 to sa58 sga21 1 1 0 1 x x x x x sa59 to sa62 sga22 1 1 1 0 x x x x x sa63 to sa66 sga23 1 1 1 1 00 x x x sa67 to sa69 01 10 sga24 1 1 1 1 1 1 x x x sa70
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 22 functional description simultaneous operation the device has a feature taht is capable of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). the bank selection can be selected by bank address (a 20 to a 15 ) with zero latency. the device has two banks which contain bank 1 (4 kw eight sectors, 32 kw seven sectors) and bank 2 (32 kw fifty-six sectors). the simultaneous operation cannot execute multi-function mode in the same bank. ?simultaneous operation? table shows the possible combinations for simultaneous operation. (refer to ?bank-to-bank read/write timing diagram? in ? timing diagram?.) simultaneous operation table *: erase operation may also be suspended to read from or program to a sector not being erased. read mode the device has two control functions to be satisfied for obtaining data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used as the gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time (t oe ) is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time). when reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from ?h? or ?l?. page mode read the device is capable of fast page mode read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words, within the appropriate page being selected by the higher address bits a 20 to a 2 and the lsb bits a 1 and a 0 within that page. this is an asynchronous operation with the microprocessor supplying the specific word location. the random or initial page access is equal to t acc and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to t pac c . here again, ce selects the device and oe is the output control and should be used to gate data to the output pins if the device is selected. fast page mode accesses are obtained by keeping a 20 to a 2 constant and changing a 1 and a 0 to select the specific word, within that page. case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 23 standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition, the current consumed is less than 5 a max during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = ?h?. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = ?h? or ?l?). under this condition the current consumed is less than 5 a max once the reset pin is taken high, the device requires t rh as wake up time for outputs to be valid for read access. in the standby mode, the outputs are in the high impedance state, independently of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of the device data. this mode can be useful in the application such as a handy terminal which requires low power consumption. to activate this mode, the device automatically switches themselves to low power mode when the device ad- dresses remain stable during access time of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 50 a (cmos level). during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically, and the device reads the data for changed addresses. output disable with the oe input at a logic high level (v ih ), output from the device is disa bled. this will caus e the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the devi ce and will identify its manufacturer and type. this mode is intended for use by programmin g equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (10.0 v to 11.0 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are don?t cares except a 6 , a 3 , a 2 , a 1 , and a 0 . (see ?mbm29pds322te/be user bus operations? table in ? device bus operation?.) the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in ?mbm29pds322te/be co mmand definitions? table in ? device bus operation?. (refer to autoselect command section.) in the command autoselect mode, the bank addresses ba; (a 20 to a 12 ) must point to a specific bank during the third write bus cycle of the autosele ct command. then the au toselect data will be re ad from that bank while array data can be read from the other bank. a read cycle from address (ba)00h returns the manufacturer?s code (f ujitsu = 04h). and a read cycle from address (ba)01h, (ba)0eh to (ba)0fh returns the device code. (see mbm29pds322te?s/be?s ?sector group protection verify autoselect codes? tables and ?expanded autoselect code? tables in ? device bus oper- ation?.) in case of applying v id on a 9 , since both bank 1 and bank 2 enter autoselect mode, the simultaneous operation can not be executed.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 24 write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector group protection the device features hardware sector group protection. this feature will disable both progra m and erase opera- tions in any combination of twenty five sector groups of memory. (see mbm29pds322te?s/be?s ?sector group address? tables in ? flexible sector-erase architecture?.) the sector group protection feature is enabled using programming equipment at the user?s site. the device is shipped with all sector groups unpro- tected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0). the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. ?sector address? tables (mbm29pds322te and mbm29pds322be) in ? flexible sector-erase architecture? de fine the sector address for each of the seventy one (71) individual sectors, and ?sector group address? tables (mbm29pds322te and mbm29pds322be) in ? flexible sector-erase architecture? de fine the sector group address for each of the twenty five (25) individual group sectors. programming of th e protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see ?sector group protection timing diagram? in ? timing diagram? and ?sector group protection algorithm? in ? flow charts? for sector group protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a lo gical ?1? code at device output dq 0 for a protected sector. otherwise the device will produce ?0? for unpr otected sector. in this mode, the lower order addresses, except for a 0 , a 1 , a 2 , a 3 , and a 6 are don?t cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group addr ess will produce a logical ?1? at dq 0 for a protected sector group. see mbm29pds322te?s/be?s ?sector group protection verify autoselect codes? tables and ?expanded autoselect code? tables in ? device bus operation? for autoselect codes. temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the device in order to change data. the sector group un protection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad- dresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to ?temporary sector group unprotection timing diagram? in ? timing diagram? and ?temporary sector group unprotection algorithm? in ? flow charts?.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 25 extended sector group protection in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables to protect sector group by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (recommend to set v il for the other addresses pins), and write extended sector group protection command (60h). a sector group is typically protected in 250 s. to verify programming of the protection circuitry, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set and write a command (40h). following the command write, a logical ?1? at device output dq 0 will produce for protected sector in the read operation. if the output is logical ?0?, please repeat to write extended sector group protection command (60h) again. to te rminate the operation, it is necessary to set reset pin to v ih . (refer to ?extended sector group protection timing diagram? in ? timing diagram? and ?extended sector group protection algorithm? in ? flow charts?.) reset hardware reset the device may be reset by driving the reset pin to v il . the reset pin vs. a pulse requirement and has to be kept low (v il ) for at least ?t rp ? in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the intern al state machine will be reset to the read mode ?t ready ? after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional ?t rh ? before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and a ll the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that pa rticular location will be corrupte d. please note that the ry/by output signal should be ignored during the reset pulse. see ?reset , ry/by timing diagram? in ? timing diagram? for the timing diagram. refer to temporary sector group unprotection for additional functionality. boot block sector protection the write protection function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables prog ram and erase functions in the two ?outermost? 4k word boot sectors independently of whether those sectors are protected or unprotected using the method described in ?sector protection/unprotection?. the two outermost 4k word boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (mbm29pds322te: sa69 and sa70, mbm29pds322be: sa0 and sa1) if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 4k word boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in ?sector protection/unprotection?. accelerated program operation the device offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to abo ut 60%. this function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 26 acceleration mode, the device automatically set to fast mode. therefore, the present sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see ?accelerated program timing diagram? in ? timing diagram?. erase operation during accalerated program operation is strictly prohibited.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 27 command definitions the device operations are selected by writing specific address and data sequences into the command register. some commands require bank address (ba) input. when command sequences are inputted to bank being read, the commands have priority over reading. ?mbm29pds322te/be command definitions? table in ? device bus operation? defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. micro- processor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this ca se, a command sequenc e is not required to read data. standar d microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read character- istics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by firstly writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and actual data of memory cell can be read from the another bank. following the command write, a read cycle from address (ba)00h retrieves the manufacture code of 04h. a read cycle at address (ba)01h returns 7eh to indicate that this device uses extended device code. the successive read cycle from (ba)0eh to (ba)0fh re turns this extended device code fo r this device. (see mbm29pds322te?s/ be?s ?sector group protection verify autoselect codes? tables and ?expanded autoselect code? tables in ? device bus operation?.) the sector state (protection or un protection) will be informed by addr ess (ba)02h. scanni ng the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical ?1? at device output dq 0 for a protected sector group. the programming verification should be performed by verify sector group protection on the protected sector. (see ?mbm29pds322te/be user bus operations? ta b l e i n ? device bus operation?.) the manufacture and device codes can be allowed to read from selected bank. to read the manufacture and device codes and sector protection status from non-sel ected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the flash memory, the device and manu- facture codes should be read from the other bank which doesn?t contain the software. to terminate the operation, it is necessary to write the read/reset command sequence into the register. to execute the autoselect command during the operation, writing read/reset command sequence must precede the autoselect command.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 28 word programming the device is programmed on a word-by-word basis. programming is a four bus cycle operation. there are two ?unlock? write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the fa lling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device automatically provides adequate internally generated program pulses and verify programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the data polling and toggle bit must be performe d at the memory location being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which the device returns to the read mode and addresses are no longer latched. (see ?hardware sequence flags? table.) therefore the device requires that a valid address to the device be supplied by the system at this particular moment. hence data polling must be performed at the memo ry location which is being programmed. if hardware reset occurs during the programming operation, it is impossible to guarantee the data being written. programming is allowed in any sequence and across sector boundaries. beware that a data ?0? cannot be programmed back to a ?1?. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still ?0?. only erase operations can convert ?0?s to ?1?s. ?embedded program tm algorithm? in ? flow charts? illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command seque nce the device will automatically program an d verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is ?1? (see write operation status section.) at which the device returns to read the mode. chip erase time : sector erase time all sectors + chip program time (preprogramming) ?embedded erase tm algorithm? in ? flow charts? illustrates the embedded erase tm algorithm using typical command strings and bus operations.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 29 sector erase sector erase is a six bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the sector erase command. the sector address (any address location within the desired sect or) is latched on the falling edge of ce or we whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we which happens first. after time-out of ?t tow ? from the rising edge of the last sector erase command, the sector erase operation begins. multiple sectors are erased concurrently by writing the six bus cycle operations on ?mbm29pds322te/be command definitions? table in ? device bus operation?. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than ?t tow ? otherwise that command will not be acce pted and erasure do es not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of ?t tow ? from the rising edge of last ce or we whichever happens first will initia te the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the ?t tow ? time-out window the timer is reset. (monitor dq 3 to determine if the sector erase ti mer window is still open, see section dq 3 , sector erase timer.) resetting the device once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prio r to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the sector erase begins after the ?t tow ? time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is ?1? (see write operation status section.) at which time the device returns to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time : [sector erase time + sector program time (preprogramming)] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform. ?embedded erase tm algorithm? in ? flow charts? illustrates the embedded erase tm algorithm using typical command strings and bus operations.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 30 erase suspend/resume the erase suspend command allows the user to interrupt sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. writing the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erased or erase-suspended should be set when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device takes a maximum of ?t spd ? to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin is at hi-z and the dq 7 bit is at logic ?1?, and dq 6 stops toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation is suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the device is in the eras e-suspend-progra m mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of th e resume command at this point w ill be ignored. a nother erase suspend command is written after the chip has resumed erasing. extended command (1) fast mode the device has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for progra mming is two cycles instead of fo ur bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. in continuous mode, do not write any command other than the continuous program/continuous mode reset command. to exit this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to ?embedded program tm algorithm for fast mode? in ? flow charts?.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to ?embedded program tm algorithm for fast mode? in ? flow charts?.)
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 31 hiddenrom region the hiddenrom feature provides flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. on ce the hiddenrom region is protected, any further modification of that region is not allowed. this ensures the security of the esn once the product is shipped to the field. the hiddenrom region is 32 k words in length and is stored at the same address as the 4 kw 8 sectors. the mbm29pds322te occupies the address of the word mode 1f8000h to 1fffffh and the mbm29pds322be type occupies the address of the wo rd mode 000000h to 007 fffh. after the system writes the enter hiddenrom command sequence, the system reads the hiddenrom re gion by using the address es normally occupied by the boot sectors. that is, the device sends all commands that would normally be sent to the boot sectors to the hiddenrom region. this mode of operation continues until the system issues the exit hiddenrom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. when reading the hiddenrom region, either change addresses or change ce pin from ?h? to ?l?. the same procedure should be taken (changing addresses or ce pin from ?h? to ?l?) after the system issues the exit hiddenrom command sequence to read actual data of memory cell. hiddenrom entry command the device has hiddenrom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. program/erase is possible in this area until it becomes protected. however once it is protected, it is impossible to unprotect, use this command with caution. hiddenrom area is 32 k words and in the same address area as 4 kw sector. the address of top boot is 1f8000h to 1fffffh at word mode and the bottom boot is 000000h to 007fffh at word mode. these areas are normally the boot block area (4 kw 8 sector). therefore write the hiddenrom entry command sequence to enter the hiddenrom area. this is called hiddenrom mode as the hiddenrom area appears. sector other than the boot block area could be read during hiddenrom mode. read/program/erase of the hiddenrom area is allowed during hiddenrom mode. write the hiddenrom reset command sequence to exit the hiddenrom mode. the bank address of the hiddenrom should be set on the third cycle of this reset command sequence. note that any other commands sh ould not be issued than the hiddenrom program/ protection/reset commands during the hiddenrom mode . when you issue the other commands including the suspend resume capability, send the hiddenrom reset command first to exit the hiddenr om mode and then issue each command. hiddenrom program command to program data to the hiddenrom area, write the hiddenrom program command sequence during hidden- rom mode. this command is the same as the program command in usual except to write the command during hiddenrom mode. therefore the detection of completion method is the same as described, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. it is necessary to pay attention to the address to be programmed. if the address other than the hiddenrom ar ea is selected to program, data of the address will be changed. during the write into the hiddenrom region, the program suspend command issuance is prohibited. hiddenrom erase command to erase the hiddenrom area, write the hiddenrom erase command sequence during hiddenrom mode. this command is same as the sector erase command in the past except to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. it is necessary to pay attention to the sector address to be erased. if the sector address other than the hiddenrom area is selected , the data of the se ctor will be changed.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 32 hiddenrom protect command there are two methods to protect the hiddenrom area. one is to write the sector group protect setup command (60h), set the sector address in the hiddenrom area and (a 6 , a 3 , a 2 ,a 1 , a 0 ) = (0,0,0,1,0), and write the sector group protect command (60h) during the hiddenrom mode. the same command sequence could be used because, it is just as the extension sector group protect in the past except that it is in the hiddenrom mode and it does not apply high voltage to reset pin. please refer to ?function explanation extended sector group protection? for details of extension sector group protect setting. the other method is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0), and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) and the sector address in the hiddenrom area, and read. when ?1? appears on dq 0 , the protect setting is completed. ?0? will appear on dq 0 if it is not protected. please apply write pulse again. the same command sequence could be used for the above method because other than the hiddenrom mode, it is the same with the sector group protect previously mentioned. refer to ?function explanation sector group protection? for details of the sector group protect setting. other sector group will be effect ed if the address ot her than those for hiddenrom ar ea is selected for the sector group address. once it is protected, protection cannot be cancelled, so please pay the closest attention. write operation status detailed in ?hardware sequence flags? table are all the st atus flags that determine the status of the bank for the current mode operation. the read operation from the bank which does not operate embedded algorithm returns data of memory cells. these bits offer a method for determining whether a embedded algorithm is properly completed. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consecutively read, then the dq 2 bit will toggle. however dq 2 will not toggle if an address from a non- erasing sector is consecutively read. this allows users to determine which sectors are in erase. the status flag is not output from bank (non-busy bank) which does not execute embedded algorithm. for example, there is bank (busy bank) , now executing embedded algorithm. when the read sequence is [1] , [2] , [3] , the dq 6 is toggling in the case of [1] and [3]. in case of [2], the data of memory cells are outputted. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in the [1] and [3]. in the erase suspend read mode, dq 2 is toggled in the [1] and [3]. in case of [2], the data of memory cell is outputted.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 33 hardware sequence flags table *1: successive reads from the erasing or erase-suspend sector causes dq 2 to toggle. *2: reading from non-erase su spend sector address will in dicate logic ?1? at the dq 2 bit. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle * 1 erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase susp ended sector) data data data data data erase suspend program (non-erase susp ended sector) dq 7 toggle 0 0 1 * 2 program suspende mode program suspend read (program suspended sector) data data data data data program suspend read (non-program suspended sector) data data data data data exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase susp ended sector) dq 7 toggle 1 0 n/a
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 34 dq 7 data polling the device features data polling as a method to indicate to th e host that the embedded algorithms are in progress or completed. during the embedded program algorithm an atte mpt to read device will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read device will produce a ?0? at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read device will produce a ?1? on dq 7 . the flowchart for data polling (dq 7 ) is shown in ?toggle bit algorithm? in ? flow charts?. for programming, the data polling is valid after the rising edge of th e fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address of sectors being erased, not protected sectors. otherwise, the status may be invalid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 s, then the bank returns to read mode. once the embedded algorithm operation is close to completion, the device data pins (dq 7 ) may change asyn- chronously while the output enable (oe ) is asserted low. this means that device is driving status information on dq 7 at one instant of time and then that byte?s valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if device has completed the embedded algorithm operation and dq 7 has a valid data, data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is active only during the embedde d programming algorithm, embedded erase algorithm or sector erase time-out. (see ?hardware sequence flags? table.) see ?toggle bit i during embedded algorithm operation timing diagram? in ? timing diagram? for the data polling timing specifications and diagrams. dq 6 to g g l e b i t i the device also features the ?toggle bit i? as a method to indicate to the host system that the embedded algorithms are in progress or completed. during embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will results in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during pro- gramming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector be ing written is protecte d, the toggle bit will toggle for about 1 s and then stop toggling with data unchanged. in erase, device will erase a ll selected sectors except fo r ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data unchanged. either ce or oe toggling will cause dq 6 to toggle. in addition, an eras e suspend/resume command will cause dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erased or is erase-suspended. when a bank is actively erased (that is, the embedded erase algorithm is in progress), dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during erase-suspend-program cause dq 6 to toggle.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 35 to operate toggle bit function properly, ce or oe must be high when bank address is changed. see ?bank-to-bank read/write timing diagram? in ? timing diagram? for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has ex ceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a ?1?. this is a failure conditio n which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of device under this condition. the ce circuit will partially power down device under th ese conditions (to approximately 2 ma). the oe and we pins will control the output disabl e functions as described in ?sim ultaneous operation? table in ? func- tional description?. the dq 5 failure condition may also appear if a user tries to program a non blank location without pre-erase. in this case the device locks out and never complete the embedded algorithm operation. hence, the system never read valid data on dq 7 bit and dq 6 never stop toggling. once device has exceeded timing limits, the dq 5 bit will indicate a ?1.? please note that this is not a device failure condition since device was incorrectly used. if this occurs, reset device with command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence sect or erase time-out will begin. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid af ter the initial sector erase command sequence. if data polling or the toggle bit i indicates device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (?1?) the internally controlled erase cycle has begun.if dq 3 is low (?0?), the device will accept additi onal sector erase comm ands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see ?hardware sequence flags? table. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successi ve reads from the erase- suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the word address of the non-erase suspended sector will indica te a logic ?1? at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also and. furthermore, dq 2 can also be used to determine which sector is being erased. when device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 36 reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device ha s completed the program or er ase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ). if it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still togg ling, the device did not comp lete the operation successfully , and the system must write the reset command to return to reading array data. the remaining scenario is that th e system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragrap h. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to ?toggle bit algorithm? in ? flow charts?.) toggle bit status table *1: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2: reading from the non-erase suspend sector address will indicate logic ?1? at the dq 2 bit. ry/by ready/busy the device provides a ry/by open-drain output pin as a way to indicate to the host system that embedded algorithms are either in progress or has been completed. if output is low, device is busy with either a program or erase operation. if output is high, device is ready to accept any read/write or erase operation. if the device is placed in an erase suspend mode, ry/by output will be high. during programming, ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, ry/by pin is driven low after the rising edge of the sixth write pulse. ry/by pin will indicate a busy condition during reset pulse. refer to ?ry/by timing diagram during program/erase operation timing dia- gram? and ?reset , ry/by timing diagram? in ? timing diagram? for a detailed timing diagram. ry/by pin is pulled high in standby mode. since this is an open-drain output, the pull-up resistor needs to be v cc ; multiples of devi ces may be connected to the best system via more than one ry/by pin in parallel. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle * 1 erase-suspend read (erase-suspended sector) 1 1 toggle erase-suspend program dq 7 toggle 1 * 2
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 37 data protection the device is designed to offer protection against accide ntal erasure or programming caused by spurious system level signals that may exist during power transitions. during power up device automatically resets internal state machine in read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. power on/off timing the reset pin must be held low during v cc ramp up to insure that device power up correctly. (refer to ?page read operation timing diagram? in ? timing diagram?.) write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe , ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. sector protection device user is able to protect each sector group individually to store and protect data. protection circuit voids both write and erase comm ands that are addressed to protected sectors. any commands to write or erase addressed to protected sector are ignore (see ? sector group protection? in ? functional description?).
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 38 absolute maximum ratings *1: minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns. *2: minimum dc input voltage on a 9 , oe and reset pins is ?0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to ?2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc ) does not exceed +9.0v. maximum dc input voltage on a 9 , oe and reset pins is +11.0 v which may positive overshoot to + 12.5 v for periods of up to 20 ns. *3: minimum dc input voltage on wp /acc pin is ?0.5 v. during voltage transitions, wp /acc pin may undershoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +12.6 v which may positive overshoot to +13.0 v for periods of up to 20ns when vcc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating ranges note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg ?55 +125 c ambient temperature with power applied t a ?40 +85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1 v in , v out ?0.5 v cc +0.5 v power supply voltage * 1 v cc ?0.5 +2.7 v a 9 , oe , and reset * 2 v in ?0.5 +11.0 v wp /acc * 3 v acc ?0.5 +12.6 v parameter symbol value unit min max ambient temperature t a ?40 +85 c power supply voltage v cc +1.8 +2.2 v
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 39 maximum overshoot / maximum undershoot 0.2 v cc ? 0.5 v 20 ns ? 2.0 v 20 ns 20 ns maximum undershoot waveform v cc + 0.5 v 0.8 v cc v cc + 2.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 1 maximum overshoot waveform 2 + 11.0 v v cc + 0.5 v + 12.5 v 20 ns 20 ns 20 ns note: this waveform is applied for a 9 , oe and reset
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 40 electrical characteristics 1. dc characteristics *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc is active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: applicable for only v cc applying. *5: embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol conditions value unit min max input leakage current i li v in = v ss to v cc , v cc = v cc max ?1.0 +1.0 a output leakage current i lo v out = v ss to v cc , v cc = v cc max ?1.0 +1.0 a a 9 , oe , reset inputs leakage current i lit v cc = v cc max , a 9 , oe , reset = 11.0 v ?35 a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 10 mhz ? 28 ma ce = v il , oe = v ih , f = 1 mhz ? 3 ma v cc active current * 2 i cc2 ce = v il , oe = v ih ?30ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v ?5 a v cc current (standby, reset) i cc4 v cc = v cc max, we /acc = v cc 0.3 v, reset = v ss 0.3 v ?5 a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v ?5 a v cc active current * 5 (read-while-program) i cc6 ce = v il , oe = v ih ?55ma v cc active current * 5 (read-while-erase) i cc7 ce = v il , oe = v ih ?55ma v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih ?35ma wp /acc accelerated program current i acc v cc = v cc max, wp /acc = v acc max ?20ma input low level v il ??0.50.2 v cc v input high level v ih ?0.8 v cc v cc +0.3 v voltage for wp /acc sector protection/unprotection and program acceleration * 4 v acc ? 8.5 12.5 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id ?10.011.0v output low voltage level v ol i ol = 100 a, v cc = v cc min ? 0.1 v output high voltage level v oh i oh = ?100 av cc ?0.1 ? v low v cc lock-out voltage v lko ? 1.2 1.5 v
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 41 2. ac characteristics ? read only operations characteristics note: test conditions: output load: 30 pf (mbm29pds322te10/be10) 100 pf (mbm29pds322te11/be11) input rise and fall times: 5 ns input pulse levels: 0.0 v or 2.0 v timing measurement reference level input: 1.0 v output: 1.0 v parameter symbol conditions value(note) unit 10 11 jedec standard min max min max read cycle time t avav t rc ?100 ? 115 ? ns address to output delay t avqv t acc ce = v il , oe = v il ? 100 ? 115 ns page read cycle time ? t prc ?40 ? 50 ? ns page address to output delay ? t pacc ce = v il , oe = v il ? 40 ? 50 ns chip enable to output delay t elqv t ce oe = v il ? 100 ? 115 ns output enable to output delay t glqv t oe ? ? 35 ? 45 ns chip enable to output high-z t ehqz t df ? ? 30 ? 30 ns output enable to output high-z t ghqz t df ? ? 30 ? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ?0 ? 0 ? ns reset pin low to read mode ? t ready ? ? 20 ? 20 s c l device under test test conditions note : c l = 30 pf including jig capacitance (mbm29pds322te10/be10) c l = 100 pf including jig capacitance (mbm29pds322te11/be11)
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 42 ? write/erase/program operations (continued) parameter symbol value unit 10 11 jedec standard min typ max min typ max write cycle time t avav t wc 100 ?? 115 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address setup time to oe low during toggle bit polling ?t aso 15 ?? 15 ?? ns address hold time t wlax t ah 60 ?? 60 ?? ns address hold time from ce or oe high during toggle bit polling ?t aht 0 ?? 0 ?? ns data setup time t dvwh t ds 60 ?? 60 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns output enable hold time read ?t oeh 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? ns ce high during toggle bit polling ? t ceph 20 ?? 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns write pulse width t wlwh t wp 60 ?? 60 ?? ns ce pulse width t eleh t cp 60 ?? 60 ?? ns write pulse width high t whwl t wph 60 ?? 60 ?? ns ce pulse width high t ehel t cph 60 ?? 60 ?? ns programming operation t whwh1 t whwh1 ? 16 ?? 16 ? s sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ? s v cc setup time ? t vcs 50 ?? 50 ?? s rise time to v id * 2 ?t vidr 500 ?? 500 ?? ns rise time to v acc * 3 ?t vaccr 500 ?? 500 ?? ns voltage transition time * 2 ?t vlht 4 ?? 4 ?? s write pulse width * 2 ?t wpp 100 ?? 100 ?? s oe setup time to we active * 2 ?t oesp 4 ?? 4 ?? s
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 43 (continued) *1: this does not include the preprogramming time. *2: this timing is for sector group protection operation. *3: this timing is for accelerated program operation. parameter symbol value unit 10 11 jedec standard min typ max min typ max ce setup time to we active * 2 ?t csp 4??4??s recover time from ry/by ?t rb 0??0??ns reset pulse width ? t rp 500 ? ? 500 ? ? ns reset high level period before read ? t rh 200 ? ? 200 ? ? ns program/erase valid to ry/by delay ? t busy ? ? 90 ? ? 90 ns delay time from embedded output enable ? t eoe ? ? 100 ? ? 115 ns erase time-out time ? t tow 50 ? 50 ? ? s erase suspend transition time ? t spd ? ? 20 ? ? 20 s power on / off time ? t ps ? ? 100 ? ? 115 ns
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 44 erase and programmin g performance fbga pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min typ max sector erase time ? 1 10 s excludes programming time prior to erasure word programming time ? 16 360 s excludes system-level overhead chip programming time ? ? 100 s excludes system-level overhead program/erase cycle 100,000 ? ? cycle ? parameter symbol condition value unit typ max input capacitance c in v in = 0 6.0 7.5 pf output capacitance c out v out = 0 8.5 12.0 pf control pin capacitance c in2 v in = 0 7.5 9.0 pf wp /acc pin capacitance c in3 v in = 0 13.0 16.0 pf
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 45 timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance "off" state address address stable high-z high-z ce oe we outputs output valid t rc t acc t oe t df t ce t oh t oeh read operation timing diagram
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 46 address ce reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh hardware reset/read op eration timing diagram
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 47 output high-z a 0 to a 1 a 2 to a 20 ce oe we aa ab ac t rc t acc t ce t oe t oh t oh t oh t df t pacc t pacc t oeh t prc da db dc same page address page read operation timing diagram
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 48 t ch t cs t wp t whwh1 t wc ce oe t rc address data t ghwl t ce t oe t wph t ds t dh dq 7 pd a0h d out d out we 555h pa pa t oh t as t ah 3rd bus cycle data polling t df alternate we controlled program operation timing diagram notes: ? pa is address of the memory location to be programmed. ? pd is data to be programmed at word address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates last two bus cycl es out of four bus cycle sequence.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 49 t ws t ghel t wh t cp t whwh1 t wc t ah we oe address data t cph t ds t dh dq 7 pd a0h d out ce 555h pa pa t as 3rd bus cycle data polling alternate ce controlled program operation timing diagram notes: ? pa is address of the memory location to be programmed. ? pd is data to be programmed at word address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates last two bus cycl es out of four bus cycle sequence.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 50 v cc ce oe address data t dh we t wc t as 555h 2aah 555h 555h 2aah sa * t ghwl t wp t cs t ch t ds t vcs t wph t ah aah 10h/ 30h 55h 80h aah 55h 10h for chip erase chip/sector erase operation timing diagram *: sa is the sector address for sector erase. addresses = 555h for chip erase.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 51 t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data * d ata polling during embedded algorithm operation timing diagram *: dq 7 = valid data (the device has completed the embedded operation).
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 52 t oeh ce we oe dq 6 t oe t oes t dh * data (dq 7 to dq 0 ) dq 6 = toggle dq 6 = toggle dq 6 = stop toggle dq 7 = dq 0 data valid toggle bit i during embedded algorithm operation timing diagram *: dq 6 stops toggling (the device has completed the embedded operation).
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 53 bank-to-bank read/write timing diagram ce oe address dq t ghwl t df t oe we t wp t oeh t as ba1 read command command read read read ba2 (555h) ba2 (pa) ba2 (pa) ba1 ba1 t ce t dh t df t ds (a0h) (pd) t acc t aht t as t rc t rc t wc t rc t wc t rc t ah t ceph valid output valid input valid output valid input valid output status note: this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address corresponding to bank 1. ba2: address corresponding to bank 2. enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 * we toggle dq 2 and dq 6 with oe or ce dq 2 vs. dq 6 * : dq 2 is read from the erase-suspended sector.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 54 ce ry/by we rising edge of the last we signal t busy entire programming or erase operations ry/by timing diagram during program/ erase operation timing diagram t rp t rb t ready ry/by we reset r eset , ry/by timing diagram
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 55 reset data address valid data out t ps t ps v cc valid data in v ih 1.8 v t rh t acc 0 v 1.8 v power on / off timing diagram
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 56 sector group protection timing diagram spax: sector group addr ess to be protected spay: next sector group ad dress to be protected t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 20 , a 19 , a 18 a 17 , a 16 , a 15 a 14 , a 13 , a 12 a 6 , a 3 , a 2 , a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data spax 01h spay
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 57 unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce reset temporary sector group u nprotection timing diagram
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 58 v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out spax spax spay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 3 , a 2 , a 0 a 1 extended sector group protection timing diagram spax: sector group address to be protected spay: next sector group ad dress to be protected time-out: time-out window = 250 s (min)
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 59 wp/acc v acc v ih we ce ry/by t vlht program command sequence t vlht v cc t vcs t vaccr t vlht acceleration period accelerated program timing diagram
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 60 flow charts 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in program embedded program tm algorithm embedded algorithm
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 61 embedded erase tm algorithm embedded algorithm 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 62 dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes d ata polling algorithm *: dq 7 is rechecked even if dq 5 = ?1? because dq 7 may change simultaneously with dq 5 . va=address for programming =any of the sector address within the sector being erased during sector erase or multiple sector erases operation =any of the sector addresses within the sector not being protected during chip erase operation.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 63 dq 6 = toggle? dq 5 = 1? read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va start no no yes yes *1 read dq 7 to dq 0 addr. = va *1, *2 dq 6 = toggle? no yes fail pass read dq 7 to dq 0 addr. = va *1, *2 toggle bit algorithm va=bank address being executed embedded algorithm. *1: read toggle bit twice to determine whether it is toggling. *2: recheck toggle bit because it may stop toggling as dq 5 changes to ?1?.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 64 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group? increment plscnt read from sector group addr. = spa, a 1 = v ih a 6 = a 3 = a 2 = a 0 = v il setup sector group addr. a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih activate we pulse time out 100 s we = v ih , ce = oe = v il (a 9 should remain v id ) () () sector group protection algorithm
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 65 start perform erase or program operations reset = v id *1 reset = v ih temporary sector group unprotection completed *2 temporary sector group unprotection algorithm *1: all protected sector groups are unprotected. *2: all previously protected sector groups are protected once again.
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 66 extended sector group protection algorithm start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector protection completed protect other sector group? increment plscnt read from sector group address (addr. = spa, a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) remove v id from reset write reset command time out 250 s reset = v id wait to 4 s no yes setup next sector address device is operating in temporary sector group unprotection mode to protect secter group write 60h to secter address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to verify sector group protection write 40h to secter address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to setup sector group protection write xxxh/60h extended sector group protection entry?
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 67 embedded program tm algorithm for fast mode fast mode algorithm 555h/aah 555h/20h xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address? increment address verify data? data polling start no no yes yes set fast mode in fast program reset fast mode
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 68 ordering information part no. package access time (ns) sector architecture mbm29pds322te10pbt mbm29pds322te11pbt 63-pin plastic fbga (bga-63p-m01) 100 115 top sector mbm29pds322be10pbt mbm29pds322be11pbt 63-pin plastic fbga (bga-63p-m01) 100 115 bottom sector mbm29pds322 t e 10 pbt device number/description mbm29pds322 32 mega-bit (2 m 16-bit) cmos flash memory 1.8 v-only read, program, and erase package type pbt =63-ball fine pitc h ball grid array package (fbga) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 69 package dimension 63-pin plastic fbga (bga-63p-m01) dimensions in mm (inches). note : the values in parentheses are reference values. c 2001 fujitsu limited b63001s-c-2-2 11.00 0.10(.433 .004) .041 ?.004 +.006 ?0.10 +0.15 1.05 (mounting height) 1 2 3 4 5 6 7 8 a b c d e f g h 0.80(.031)typ (5.60(.220)) (5.60(.220)) index ball m 0.08(.003) 0.10(.004) index area 7.00 0.10 (.276 .004) (7.20(.283)) j k (63-?0.18 .002) 63-?0.45 0.05 ml (8.80(.346)) (4.00(.157)) 0.38 0.10 (.015 .004) (stand off)
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 70 memo
retired product y ds05-20889-6e_july 31, 2007 mbm29pds322te 10/11 /mbm29pds322be 10/11 71 revision history revision ds05-20889-6e july 31, 2007 the following comment is added. this product has been retired and is not reco mmended for new designs. availability of this document is retained for reference and historical purposes only.
mbm29pds322te 10/11 /mbm29pds322be 10/11 retired product y ds05-20889-6e_july 31, 2007 fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0305 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to c onsult with fujitsu sales representatives before ordering. the information, such as descrip tions of function and application circuit examples, in this document are presented solely for the purpose of reference to show exam ples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you devel op equipment incorporating the device based on such inform ation, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any dama ges whatsoever arising out of the use of the information. any information in this documen t, including descriptions of function and schematic diagrams, sh all not be construed as license of the use or exercise of any intellectual propert y right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or ot her right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as c ontemplated for gene ral use, including without limitation, ordinary industrial us e, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extrem ely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or othe r loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight cont rol, air traffic control, mass transpor t control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liab le against you and/or any third party for any claims or da mages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dama ge or loss from such failures by incorporating safety design meas ures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and othe r abnormal operating conditions. if any products described in th is document repr esent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japane se government will be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MBM29PDS322BE11PBT-E1

	To Download MBM29PDS322BE11PBT-E1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .